The present invention relates generally to deadlock avoidance in a bus fabric, and more particularly to deadlock avoidance at an interface between integrated circuits.
Few applications stress the resources of a computer systems to the extent that video does. Video capture, encoding, and the like involve huge transfers of data between various circuits in a computer system, for example, between video-capture cards, central processing units, graphics processors, systems memories, and other circuits.
Typically, this data is moved over various buses, such as PCI buses, HyperTransport™ buses, and the like, both on and between the integrated circuits that form the computer system. Often, first-in-first-out memories (FIFOs) are used to isolate these circuits from one another, and to reduce the timing constraints of data transfers between them.
But these FIFOs consume expensive integrated circuit die area and power. Accordingly, it is desirable to limit the depth of the FIFOs. Unfortunately, this means that these FIFOs may become filled and not able to accept further inputs, thus limiting system performance.
It is particularly problematic if these filled FIFOs are in a data path that forms a loop. In that case, there may be a processor, such as a graphics processor, or other circuit in the loop that becomes deadlocked, that is, unable to either receive or transmit data.
This can happen under the following conditions, for example. A first FIFO that receives data from a circuit cannot receive data because it is full. The first FIFO cannot send data to a second FIFO because the second FIFO is also full. The second FIFO similarly cannot send data because it wants to send the data to the circuit, which cannot accept it since it is waiting to send data to the first FIFO. This unfortunate set of circumstances can result in a stable, deadlocked condition.
Thus, what is needed are circuits, methods, and apparatus for avoiding these deadlocked conditions. While it may alleviate some deadlocked conditions to increase the size of the FIFOs, again there is an associated cost in terms of die area and power, and the possibility remains that an even deeper FIFO may fill. Thus, it is desirable that these circuits, methods, and apparatus not rely solely on making these FIFOs deeper and be of limited complexity.